Spur reduction technique for sampling PLL's
US8373481B2 · kind B2 · utility
3Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Dec 20, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Apr 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.