System and method of reading data using a reliability measure
US8374026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | May 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a particular embodiment, a data storage device includes a memory array including a target memory cell and one or more other memory cells. The data storage device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.