Output circuitry for minimizing spurious frequency content
US8374296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2008 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Nov 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/1646
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system including first voltage supply circuitry configured to provide a first voltage supply with spurious frequency content and second voltage supply circuitry configured to provide a second voltage supply without the spurious frequency content is provided. The system includes signal generation circuitry configured to generate a first digital signal using a clock signal and the first voltage supply and configured to cause the spurious frequency content on the first voltage supply and output circuitry configured to generate a second digital signal from the first digital signal synchronous with the clock signal using the second voltage supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.