Harmonic reject receiver architecture and mixer
US8374569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2012 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Aug 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.