Semiconductor integrated circuit and operating method thereof
US8374571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Oct 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.