Method and apparatus for reducing write cycles in NAND-based flash memory devices
US8375162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Apr 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.