Techniques for use with memory partitioning and management
US8375174B1 · kind B1 · utility
13Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Apr 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are techniques for partitioning memory. A plurality of boards is provided. Each of the plurality of boards includes a physical memory portion and a set of one or more processor. The physical memory portion in each of said plurality of boards is partitioned into a plurality of logical partitions including a global memory partition accessible by any processor on any of the plurality of boards and one or more other memory partitions configured for use by one or more processors of said each board. Each of the one or more other memory partitions not being accessible to a processor on a board other than said each board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.