Method for reducing punch-through in a transistor device

US8377783B2 · kind B2 · utility

Assignee

• SuVolta, Inc. · US

Inventors

• Lucian Shifren · San Jose, US
• Taiji Ema · Inabe, JP

Key dates

• Filing date: Sep 30, 2010
• Grant date: Feb 19, 2013
• Expiry date: Sep 30, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped layer in the stop layer of lesser depth than the stop layer. The stop layer has a lower concentration of impurities than the doped layer in order to prevent punch-through without increasing junction leakage.