SiC MOSFETs and self-aligned fabrication methods thereof
US8377812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2009 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Nov 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.