Three dimensional semiconductor memory device and method of manufacturing the same
US8377817B2 · kind B2 · utility
4Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Aug 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.