Low leakage FINFETs

US8378414B2 · kind B2 · utility

Assignee

• Atmel Corporation · US

Inventors

• Gayle W. Miller · Colorado Springs, US
• Volker Dudek · Ditzingen, DE
• Michael Graf · Leutenbach, DE

Key dates

• Filing date: Jun 30, 2011
• Grant date: Feb 19, 2013
• Expiry date: Aug 6, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.