Secure device anti-tampering circuit
US8378710B1 · kind B1 · utility
16Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Sep 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/07372
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments relate to an anti-tampering circuit for a secure device including: a signal delay detector; a clock delay detector; a clock duty cycle detector; and a protection unit that receives an error indication from the signal delay detector, clock delay detector, and the clock duty cycle detector, wherein the protection unit indicates tampering to a secure device upon receiving the error indication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.