Digital filter circuit
US8378713B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Sep 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a digital filter circuit includes an EXOR circuit, a clock gating circuit, a reset control circuit, a counter, a filter time setting circuit, a comparator, and a decoder. The clock gating circuit outputs a clock gating signal. The reset control circuit generates a first signal. The counter generates a count signal. The filter time setting circuit latches the count signal when the first signal is in the enable state, and outputs a latched count value as a second signal. The comparator receives the count signal and the second signal, and outputs a third signal of the enable state when the value of the count signal and the value of the second signal match each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.