5V tolerant circuit for CML transceiver in AC-couple
US8378714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Aug 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45101
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads. Further provided is a bias isolating circuit so that an input bias voltage is isolated from a high voltage in the pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.