Patent · US Active

Programmable high-speed frequency divider

US8378719B1 · kind B1 · utility

9Cited by

7References

17Claims

0Family size

Assignee

ST-ERICSSON SA · CH

Inventor

Ferdinando Pace · Birmensdorf, CH

Key dates

Filing date	Oct 18, 2011
Grant date	Feb 19, 2013
Priority date	—
Expiry date	Oct 18, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03K23/66
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A programmable high-speed frequency divider architecture is provided to provide a substantially 50% duty cycle signal output regardless of whether the division ratio is odd or even. The programmable frequency divider circuit receives an input clock signal having a first period and outputs and output clock signal that has a second clock signal period that is a programmable multiple, A, of the first period. The frequency divider includes a shift register that receives the input clock signal and produces a first output signal. The frequency divider also includes a duty cycle compensation circuit that accepts the first output signal and produces an output clock signal that has a duty cycle that is substantially 50%.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.