Fast data weighted average circuit and method
US8378869B2 · kind B2 · utility
6Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Oct 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.