Semiconductor integrated circuit device
US8379425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Apr 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.