Semiconductor device and structure
US8379458B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Jun 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells by applying an electrical signal to collector regions of multiplicity of said memory cells in parallel, wherein said collector region of said memory cells in a row of said memory array is connected to a common control line, wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein at least one of said memory cells further comprises another memory cell on top thereof; and wherein said holding operation maintains charges stored in said floating body region of multiplicity of memory cells connected to said common control line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.