Technique for fast power estimation using probabilistic analysis of combinational logic
US8380656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2009 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Aug 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.