Relocatable interrupt handler for test generation and execution
US8381040B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2009 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Nov 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A relocatable interrupt handler for use in test generation and execution. A method for executing test code includes executing a test code block that includes a plurality of test instructions. The executing includes, for one or more of the test instructions: executing the test instruction; determining that the executing the test instruction caused an exception condition to occur; executing first exception handling logic associated with the exception condition based on determining that the executing the test instruction caused the exception condition to occur, the first exception handling logic located at an entry address consisting of a first memory address value, the executing the first exception handling logic including: clearing the exception condition; and changing the entry address to a second memory address value that is an address of a second exception handling logic. A return code that indicates a result of executing the test code block is then generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.