Simplified LDPC encoding for digital communications
US8381079B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2008 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Dec 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/255
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.