System and method of test mode gate operation
US8381144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Nov 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a method includes, after a layout phase of generating a design of a circuit, receiving timing information related to the design of the circuit. The method also includes selectively identifying at least one gate of a combinational logic portion of the design of the circuit to be modified to respond to a test enable signal, the at least one gate identified at least partially based on the timing information. The method also includes modifying the at least one gate. The at least one modified gate is fixed at a constant level during a test mode and is dynamically changeable during a functional mode of operation of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.