Patent · US Active

Method and system for model-based design and layout of an integrated circuit

US8381152B2 · kind B2 · utility

9Cited by

41References

33Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Ya-Chieh Lai · Mountain View, US
Frank E. Gennari · Berkeley, US
Matthew W. Moskewicz · Berkeley, US
Srinivas Doddi · Fremont, US
Junjiang Lei · Fremont, US
Weiping Fang · Fremont, US
Kuanghao Lay · Mountain View, US

Key dates

Filing date	Jun 5, 2008
Grant date	Feb 19, 2013
Priority date	—
Expiry date	Nov 20, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.