3D inter-stratum connectivity robustness
US8381156B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2011 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Aug 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.