Patent · US Active

System and method for monotonic partial order reduction

US8381226B2 · kind B2 · utility

4Cited by

2References

6Claims

0Family size

Assignee

NEC Laboratories America, Inc. · US

Inventors

Vineet Kahlon · Princeton, US
Chao Wang · Los Angeles, US
Aarti Gupta · Princeton, US

Key dates

Filing date	Feb 6, 2009
Grant date	Feb 19, 2013
Priority date	—
Expiry date	Dec 23, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method for analyzing concurrent programs that guarantees optimality in the number of thread inter-leavings to be explored. Optimality is ensured by globally constraining the inter-leavings of the local operations of its threads so that only quasi-monotonic sequences of threads operations are explored. For efficiency, a SAT/SMT solver is used to explore the quasi-monotonic computations of the given concurrent program. Constraints are added dynamically during exploration of the concurrent program via a SAT/SMT solver to ensure quasi-montonicity for model checking.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.