Three-dimensional semiconductor memory device and method of fabricating the same
US8383482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Apr 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.