Battery state monitoring circuit and battery device
US8384355B2 · kind B2 · utility
3Cited by
1References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Sep 6, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Provided are a battery state monitoring circuit and a battery device that are capable of reliably controlling charge by a charger even if a voltage of a secondary battery drops to around 0 V. In the battery device provided with the battery state monitoring circuit, respective gate voltages of a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor, which together form a voltage detection circuit for detecting a voltage of around 0 V of the secondary battery, are applied by a voltage dividing resistor circuit that is connected across terminals of the secondary battery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.