Configuring multiple programmable logic devices with serial peripheral interfaces
US8384427B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Apr 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable logic device includes configuration memory, an SPI port for receiving a bitstream, a chip select output pin, and configuration control circuitry. The chip select output pin can provide a chip select signal having a first logic state for selecting another device (such as another PLD) to receive a bitstream and a second logic state for de-selecting the other device. The configuration control circuitry is responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state, thereby selecting the other device to receive the bitstream. Several such PLDs connected in a daisy chain can thus be configured from a single configuration source or have their configuration data read back while so connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.