Integrated jitter compliant low bandwidth phase locked loops
US8384452B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2011 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Sep 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.