Low jitter clock interpolator
US8384464B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2011 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Low jitter clock interpolator circuits in accordance with embodiments of the invention are illustrated. In many embodiments, the low jitter clock interpolator incorporates a time based numerically controlled oscillator (NCO) to generate a clock signal, and different phases of the resulting clock are created using a clock interpolator. Information from the time based NCO and the interpolator is then used to select phases and create an output clock that is jitter free within the precision of the interpolator. One embodiment of the invention includes a time based numerically controlled oscillator (NCO) configured to produce a NCO output in response to a high speed clock (hsclk) input and a frequency control word (FCW), where the output periods of the NCO output are integer multiples of the hsclk period and the average output period of the NCO output corresponds to the FCW, a clock interpolator circuit configured to receive the NCO output and the hsclk input and to generate a plurality of different phases of the NCO output, and a phase calculator circuit configured to select phases generated by the clock interpolator to produce a low jitter clock signal output having an output period t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.