Memory circuit and method of operating the same
US8385136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Apr 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.