Patent · US Active

Apparatus and method for multi-level cache utilization

US8386701B2 · kind B2 · utility

1Cited by

18References

9Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Raymond S. Tetrick · Portland, US
Dale Juenemann · North Plains, US
Robert Brennan · Dunstable, GB

Key dates

Filing date	Apr 19, 2012
Grant date	Feb 26, 2013
Priority date	—
Expiry date	Apr 19, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C2211/5641
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.