Writing to memory using shared address buses
US8386739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2009 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Jan 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.