High speed redundant data processing system
US8386843B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Oct 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1645
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed data processing system is described comprising first and second data processing modules and first and second data checking modules. The first and second data processing modules are each arranged to perform substantially the same processing steps on data received at said data input, with each providing an output. The first and second checking modules are arranged to compare the outputs of said first and second data processing modules and to output an error signal indicative of whether or not said first and second data processing modules have performed substantially the same processing steps. The first and second checking modules are located on physically separate devices. In some arrangements a third checking module is provided, which checking module may be physically separated from each of said first and second checking modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.