Computer memory test structure
US8386867B2 · kind B2 · utility
7Cited by
14References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2009 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Sep 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.