Patent · US Active

Cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation

US8386897B1 · kind B1 · utility

3Cited by
3References
15Claims
0Family size

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Key dates

Filing dateMay 30, 2012
Grant dateFeb 26, 2013
Priority date—
Expiry dateMay 30, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03M13/373
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.