Integrated circuits design
US8386980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Dec 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention concerns an automated method of generating a design for an I/O fabric of a target integrated circuit having a core and pins. A process tool executes algorithms to generate a synthesizable representation of the I/O fabric ring in hardware description language. It imports integrated circuit design data, and from it captures I/O specification data for a circuit core, library of cells, pin, I/O control, BSR and I/O cell chaining, and die. The tool validates the specification data, and generates the I/O fabric design by configuring and inter-connecting a pin multiplexing and control matrix structures according to constraints for signal control, and timing. The structures includes on both the input and output paths of each pin a functional multiplexer matrix structure, a test multiplexer matrix structure, an override matrix structure, a multiplex select and control matrix structure, and an I/O Cell control logic. A required pin output circuit is configurable by modification of the I/O specification data, and/or, modification of a manner of wiring the algorithms, and/or by modification of the algorithms. The tool wires algorithms according to a wiring framework, and said wi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.