Method and systems for implementing I/O rings and die area estimations
US8386981B1 · kind B1 · utility
3Cited by
35References
49Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Mar 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.