Semiconductor device
US8390046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2010 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Jul 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.