Supplying a clock signal and a gated clock signal to synchronous elements
US8390328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2011 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | May 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The circuitry receives a clock signal, a clock enable signal having either an enable value or a disable value, and a power mode signal having either a low power value (indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down), or a functional mode value (indicating the plurality of synchronous elements are to be powered). A clock gating unit has logic circuitry that is configured to output the clock signal or the predetermined gated value depending upon the low power value and the functional mode value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.