Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line
US8390352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2009 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Aug 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.