Integrated jitter compliant clock signal generation
US8390358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2010 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.