Digital background calibration in pipelined ADCS
US8390489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2009 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital background calibration in a pipelined ADC is performed by extracting a capacitor mismatch value Δ that represents a mismatch between a sampling capacitor C1 and a feedback capacitor C2 in the pipelined ADC, and using Δ to correct the capacitor mismatch error. Δ is extracted by performing commutated feedback capacitor switching (CFCS) in a background correlation loop. The error caused by the capacitor mismatch is calibrated out by subtracting the error from a digital output Dout of the pipelined ADC. Convergence speed may be accelerated and convergence accuracy may be increased during digital background calibration of pipelined ADCs, by using a higher order LPF. A bandwidth switching scheme may be implemented by the LPF, i.e. a larger bandwidth may be utilized during calibration start-up to increase convergence speed during start-up and a smaller bandwidth may be utilized during steady state to increase convergence accuracy during steady state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.