Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set
US8392641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2010 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | May 24, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.