Cache system including a plurality of processing units
US8392660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2009 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | May 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/271
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache system includes processing units operative to access a main memory device, caches coupled in one-to-one correspondence to the processing units, and a controller coupled to the caches to control data transfer between the caches and data transfer between the main memory and the caches, wherein the controller includes a memory configured to store first information and second information separately for each index, the first information indicating an order of oldness of entries in each one of the caches, and the second information indicating an order of oldness of entries for the plurality of the caches, and a logic circuit configured to select an entry to be evicted and its destination in response to the first and second information when an entry of an index corresponding to an accessed address is to be evicted from a cache corresponding to the processing unit that accesses the main memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.