Method, device, and digital circuitry for providing a closed-form solution to a scaled error locator polynomial used in BCH decoding
US8392806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2010 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Oct 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/658
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes. Having determined the value of each coefficient in the scaled error locator polynomial, one or more roots of the scaled error locator polynomial are obtained. Each of the one or more roots indicates a position of an error bit. A BCH …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.