Semiconductor device and layout design method for the same
US8392856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2011 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Aug 12, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.