Methods and systems for barrier reduction in parallel processing systems
US8392900B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | May 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods according to the present invention provide techniques which modify programs having barrier statements. Dependence relations between statements, and enforcement associations between the barrier statements and the dependence relations, in the program are identified. The dependence relations are classified as being either enforceable by point-to-point synchronization or not enforceable by point-to-point synchronization. A subset of the barrier statements, which will enforce those dependence relations that are unenforceable by point-to-point synchronization, are determined. Other(s) of the barrier statements are replaced with a point-to-point synchronization routine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.