Compiling apparatus
US8392905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Jan 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention effectively utilizes auxiliary registers and provides a compiler system which secures error detectability when the auxiliary registers are shared for plural uses. The instruction definition resource configuring unit configures, as preparation for processing by the register assigning unit, respective resources such as a register to be defined or referred to by for each instruction in an intermediate code. The instruction definition resource configuring unit detects possibility of instructions each of which is to be decomposed into plural instructions. As for an instruction to be possibly decomposed, the instruction definition resource configuring unit configures a corresponding register in the intermediate code, assuming the corresponding register used for the decomposition to be defined and referred. The register assigning unit uses the register as a general register as far as a live range of the register used for the decomposition does not overlap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.