Method and system for manufacturing copper-based capacitor
US8395200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Nov 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a capacitor on an integrated circuit includes providing an inter-metal dielectric layer on a substrate, a bottom layer having a first and second portions, a first insulating layer having via plug openings on the bottom layer, and via plugs disposed in the via plug openings. The via plugs include a first and second via plugs and are electrically coupled to the first portion of the bottom layer. The method further includes providing a capacitor layer having a first barrier metal layer coupled to the first via plug. The capacitor layer also has a capacitor dielectric layer overlying the first barrier metal layer and a second barrier metal overlying the capacitor dielectric layer. The method further includes defining a first and second capacitor layer portions. The first capacitor layer portion has two opposite sides and spacers disposed on their surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.